FIG. 1 (Prior Art) is a diagram of system 1 involving a type of analog integrated circuit 2 and a microcontroller integrated circuit 3. Analog integrated circuit 2 is sometimes called a “Power Management Unit” or “PMU”. It is desired to be able to design and fabricate such a PMU for a custom application in a small amount of time. The custom application may, for example, require that PMU 2 include a number of different types of analog circuits. The analog circuits are designed and laid out so that they pack together and are of irregular shapes as illustrated in FIG. 1. Parts of the analog circuits may be shared. One example of such an analog circuit is a voltage regulator. The voltage regulator might be configurable to output a selectable voltage. The voltage regulator might be configurable so that a current limit of the regulator can be changed. The various analog circuits of PMU 2 might be configurable such that if PMU 2 is configured in one fashion, then certain of the analog circuits are coupled to certain of the integrated circuit input/output (I/O) terminals, whereas if PMU 2 is configured in another fashion then the analog circuits are coupled to others of the I/O terminals. Each of the analog circuits of PMU 2 may, for example, be configurable so that it can be enabled or disabled. There are many ways that the various analog circuits of an analog integrated circuit such as PMU 2 may be designed to be configurable.
In the illustrated example of FIG. 1, PMU 2 includes a block 4 of non-volatile memory. The data content of particular memory cells in block 4 control corresponding particular parts of the various analog circuits of PMU 2. Typically, the designer of PMU 2 determines early in the design process the amount of nonvolatile memory that will be required to store the required configuration information. A semiconductor fabrication process is selected that has the capability of making block 4 of non-volatile memory cells. Once the amount of required non-volatile memory is known, the designer selects an adequately large predesigned block of non-volatile memory. The designer designs and lays out the remainder of the PMU integrated circuit but may leave a blank space in the layout where the chosen predesigned block 4 will be placed. At final layout time, the predesigned and characterized block 4 is instantiated into the layout to occupy the blank space. The PMU integrated circuit is then fabricated so that predesigned block 4 of non-volatile memory is part of the overall integrated circuit 2.
In the example illustrated in FIG. 1, microcontroller 3 can write configuration data into block 4 across bus 5 and using bus interface block 6. Microcontroller 3 causes a pulse of a programming voltage (VPP) to be supplied to PMU 2 via circuit 7 and conductor 8. There are multiple ways of providing this programming voltage signal. Block 7 and conductor 8 is just one way.
The configuration data that is written into block 4 controls and configures the various analog circuits of PMU 2. Thereafter, PMU 2 uses the contents of block 4 to configure its various analog circuits in an appropriate manner for the particular application to which integrated circuit 2 is put. Thereafter, if system 1 is powered down and then powered up again, the contents of non-volatile memory block 4 are used to configure PMU 2 without microcontroller 3 having to perform any additional writes to block 4. Microcontroller 3 can, however, update or change the configuration information stored in block 4 if required.
The conventional design process set forth above has several problems. First, non-volatile memory block 4 is of a design that is generally optimized for bulk data storage purposes. The non-volatile memory block may, for example, have small memory storage cells that require associated sense amplifiers. Block 4 typically involves address decoders to access a large array of such small cells. This associated address decoder and sense amplifier circuitry may be appropriate for designs involving a large amount of data storage, but in cases where only a relatively small amount of configuration information is to be stored, having to provide the associated support circuitry may be inefficient.
Not only may using block 4 involve providing an undesirable amount of support circuitry, but using block 4 requires all the cells that store configuration information to be located in one location on the integrated circuit. Running data lines from this one location to the various locations in the various analog circuits to carry needed configuration information is undesirable as compared to providing the nonvolatile memory cells locally in the analog circuits and then only having to provide relatively short conductors to carry configuration information to the various analog circuits to be configured.
Another drawback of using block 4 is that the size of the block must typically be determined early in the integrated circuit design process. The size of block 4 is determined by the number of bits required to configure the various analog circuits. If, for example, it is decided late in the design process that an additional analog circuit should be provided in PMU 2, then the size of block 4 initially selected may not be large enough to store all the configuration information. Accordingly, the design process of using a predesigned block of non-volatile memory to store configuration information is inflexible and can complicate modifying the remainder of the integrated circuit.
Another drawback of using block 4 is that block 4 may be a FLASH memory whose cells must be erased in blocks or pages. If only one configuration information bit is to be changed, it may nevertheless be necessary to block erase an entire block of FLASH cells and then to rewrite the contents of all the FLASH cells in the block just to change the data value of one of the cells. Having to conduct this block erase and rewrite process is undesirably slow and cumbersome.
Another drawback of using block 4 is that the nonvolatile cells of block 4 may suffer from what is sometimes referred to as “program disturb”. If a single cell in the array is to be written, then a pulse of a programming voltage (VPP) is typically supplied to all the cells of the array. Every time such a VPP pulse is applied, a small amount of charge is transferred onto each cell in the array. Even if the data content of a cell is not being changed, the result of the cell experiencing this VPP pulse is that the charge stored on the floating gate of the cell is slowly changed. Over many such VPP pulses, the voltages on the floating gates of the cells may change over time. In some situations, the change may be of such a magnitude that data may be lost.
One last drawback of using block 4 is that a special thin tunneling gate insulator is generally required. This thin tunneling gate insulator is not provided in a standard and typical Complementary Metal Oxide Semiconductor (CMOS) semiconductor fabrication process. Fabricating FLASH cells generally involves using a special FLASH process that is more expensive than a standard CMOS process. Even though only a small amount of FLASH memory may be required, if block 4 of predesigned and precharacterized FLASH memory is selected for use in the PMU design, then the more expensive and non-standard semiconductor fabrication process must be used.